JPS6147689A - プラグインパツケ−ジ - Google Patents

プラグインパツケ−ジ

Info

Publication number
JPS6147689A
JPS6147689A JP16894084A JP16894084A JPS6147689A JP S6147689 A JPS6147689 A JP S6147689A JP 16894084 A JP16894084 A JP 16894084A JP 16894084 A JP16894084 A JP 16894084A JP S6147689 A JPS6147689 A JP S6147689A
Authority
JP
Japan
Prior art keywords
capacitor
plug
package
pads
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16894084A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0476211B2 (en]
Inventor
岩田 勇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16894084A priority Critical patent/JPS6147689A/ja
Publication of JPS6147689A publication Critical patent/JPS6147689A/ja
Publication of JPH0476211B2 publication Critical patent/JPH0476211B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Packages (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP16894084A 1984-08-13 1984-08-13 プラグインパツケ−ジ Granted JPS6147689A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16894084A JPS6147689A (ja) 1984-08-13 1984-08-13 プラグインパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16894084A JPS6147689A (ja) 1984-08-13 1984-08-13 プラグインパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS6147689A true JPS6147689A (ja) 1986-03-08
JPH0476211B2 JPH0476211B2 (en]) 1992-12-03

Family

ID=15877360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16894084A Granted JPS6147689A (ja) 1984-08-13 1984-08-13 プラグインパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS6147689A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166543A (ja) * 1987-09-29 1989-06-30 Bull Sa Vlsiのパッケージ

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8940265B2 (en) 2009-02-17 2015-01-27 Mcalister Technologies, Llc Sustainable economic development through integrated production of renewable energy, materials resources, and nutrient regimes
US9097152B2 (en) 2009-02-17 2015-08-04 Mcalister Technologies, Llc Energy system for dwelling support
US9231267B2 (en) 2009-02-17 2016-01-05 Mcalister Technologies, Llc Systems and methods for sustainable economic development through integrated full spectrum production of renewable energy

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864095A (ja) * 1981-10-14 1983-04-16 日本電気株式会社 接続用ピン付多層配線基板
JPS5954248A (ja) * 1982-09-22 1984-03-29 Fujitsu Ltd 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864095A (ja) * 1981-10-14 1983-04-16 日本電気株式会社 接続用ピン付多層配線基板
JPS5954248A (ja) * 1982-09-22 1984-03-29 Fujitsu Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166543A (ja) * 1987-09-29 1989-06-30 Bull Sa Vlsiのパッケージ

Also Published As

Publication number Publication date
JPH0476211B2 (en]) 1992-12-03

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